(1) Field of the Invention
This invention relates to electronic data storage systems. More particularly, this invention relates to the use of the processor unit to control the regeneration of a plurality of asynchronously operating dynamic memory units.
(2) Description of the Prior Art
The cross-referenced Dennard patent discloses one type of dynamic memory element which requires periodic restoration of stored information. (It is here pointed out that the terms "restoration", "regeneration", and "refreshing", are relatively interchangeable terms and are used synonymously in the present application to describe the desired function of preventing the loss of information in a dynamic memory.) According to Dennard, restoration may be interleaved with normal memory operation by using, for example, every tenth cycle of the memory to restore one of the word positions in the array. Alternatively, Dennard teaches restoration in a burst mode by interruption of normal memory operation and restoration of the information in the entire memory during the interruption. Either approach accomplishes the desired restoration satisfactorily, but both have an effect on operation of a system incorporating a memory using these schemes, since it is necessary to interfere with normal memory operation while the restoration is being carried out.
The memory cell in the Dennard patent is extremely simple, consisting of a capacitive storage element gated by a field effect transistor. Such a memory cell has great potential for use in inexpensive, large capacity integrated circuit memories, due to its inherent simplicity. To meet the goal of low cost, it is essential that a memory cell be small in integrated circuit technology. However, reductions in size result in reduction in the capacitance of the storage element. The smaller the capacitance, the more often is restoration necessary. Thus, it is readily apparent that the optimization of refresh schemes is a significant technological problem.
The cross-referenced Spampinato et al patent discloses a different type of memory cell that also requires periodic refreshing and is known as a four device memory cell. Also known in the art are memory cells having two devices or three devices and also requiring periodic refreshing. The purpose of cross-referencing the Spampinato et al patent is to point out that dynamic memories are available in various technological configurations and that the present invention relates to all such dynamically operated memories.
The problem of refreshing dynamic memories has been addressed in a large number of patents and publications suggesting improvement and optimization. For example, refer to the cross-referenced patents to Anderson et al and Behman et al. Anderson et al, U.S. Pat. No. 3,800,295 discloses a memory system including a plurality of dynamic storage memories, each controlled by its own independent refreshing means, and a processor capable of interacting with a selected memory when access to the selected memory through the processor is desired. This system allows the refresh interval for each memory to be adjusted independent of the system to the extent of the extrinsic capability of its individual characteristics. FIG. 1 of this Anderson et al patent shows the prior art in which a processor 24 is connected to a plurality of memories operating under a single refresh control and timing. FIG. 2 illustrates the technique disclosed in the patent in which a separate refresh control and timing is associated with each of the N memory units. These two techniques as well as other prior art teachings describe the details of memory operation and attempts at optimizing the time during which a dynamic memory makes itself available to the processor. They all, however, fail to address or solve the problem of synchronizing a plurality of asynchronously operating memory units.
Also known in the prior art are static memory arrays as well as techniques by which four device memory cells, for example, can be operated in a manner to appear DC stable or static to the processor. Such prior art is not discussed in detail because the present invention is directed to a technological area in which it is desired to use a dynamic memory. It is noted that all the cross-referenced patents relate to techniques by which a dynamic memory refreshes itself and is then available to the processor. As pointed out, the prior art addresses the optimization of such restoration to increase the percent availability and general utility of the memory to the processor. In this manner, the prior art appears to have addressed the refresh problem from the viewpoint of improving dynamic memory operation. Accordingly, the prior art appears to have failed to address the problem from an overall systems point of view. For this reason, the prior art appears not to have suggested a technique of tailoring refresh to the particular processor requirements. Thus, the improvements in memory refresh techniques as described in the prior art are limited by the improvement to the memory itself as opposed to the optimization of the overall processing system including a processor with a plurality of memory units.